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Related Concept Videos

Ampere-Maxwell's Law: Problem-Solving01:17

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A parallel-plate capacitor with capacitance C, whose plates have area A and separation distance d, is connected to a resistor R and a battery of voltage V. The current starts to flow at t = 0. What is the displacement current between the capacitor plates at time t? From the properties of the capacitor, what is the corresponding real current?
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Related Experiment Video

Updated: Nov 21, 2025

Deep Neural Networks for Image-Based Dietary Assessment
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Deep Neural Networks for Image-Based Dietary Assessment

Published on: March 13, 2021

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Efficient Resource-Aware Convolutional Neural Architecture Search for Edge Computing with Pareto-Bayesian

Zhao Yang1, Shengbing Zhang1, Ruxu Li1

  • 1School of Computer Science and Engineering, Northwestern Polytechnical University, Xi'an 710072, China.

Sensors (Basel, Switzerland)
|January 13, 2021
PubMed
Summary

This study introduces an efficient resource-aware search method for optimizing deep learning models on edge devices. The new approach significantly reduces inference latency without sacrificing accuracy, improving overall search efficiency.

Keywords:
Pareto-Bayesian optimizationedge computinglatency profiling modelneural architecture search

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Last Updated: Nov 21, 2025

Deep Neural Networks for Image-Based Dietary Assessment
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Deep Neural Networks for Image-Based Dietary Assessment

Published on: March 13, 2021

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Area of Science:

  • Artificial Intelligence
  • Deep Learning
  • Edge Computing
  • Computer Science

Background:

  • Deep learning on edge devices requires balancing model accuracy with computational efficiency due to resource constraints.
  • Existing methods for optimizing deep learning models for edge deployment are often labor-intensive and require extensive experimentation.
  • Automated neural architecture search (NAS) methods aim to reduce human intervention but can be inefficient, generating many suboptimal network structures.

Purpose of the Study:

  • To develop an efficient resource-aware search method for automated neural architecture design tailored for edge devices.
  • To improve the efficiency of the neural architecture search process by incorporating device-specific performance metrics.
  • To enable the customization of neural networks for specific hardware and application requirements while maintaining high accuracy and low inference latency.

Main Methods:

  • Established a network inference consumption profiling model to accurately estimate resource usage and latency for specific edge devices.
  • Proposed a resource-aware Pareto Bayesian search method, using accuracy and inference latency as constraints to guide the search direction.
  • Optimized the search space by employing cell-based structures and lightweight operations to further enhance search efficiency.

Main Results:

  • The proposed method achieved a 94.71% reduction in inference latency for the searched network structures without compromising accuracy.
  • Demonstrated an 18.18% increase in overall search efficiency compared to existing methods.
  • Successfully generated customized neural network architectures that meet specific hardware performance requirements.

Conclusions:

  • The developed resource-aware search method significantly enhances the efficiency of designing accurate and low-latency deep learning models for edge devices.
  • This approach effectively addresses the trade-off between accuracy and efficiency in on-device deep learning.
  • The method offers a promising solution for automating and optimizing neural architecture design in resource-constrained environments.