CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Physics

Background:

• Ferroelectric memory offers advantages over flash memory in speed, power, and endurance.
• Perovskite oxide ferroelectric integration on silicon faces challenges like interfacial layers and high processing temperatures, hindering 3D integration.
• Current ferroelectric memory technologies struggle with scalability and performance limitations.

Purpose of the Study:

• To overcome the limitations of conventional ferroelectric memory integration on silicon.
• To develop a novel strategy for achieving high-performance, scalable ferroelectric memory.
• To enable unprecedented three-dimensional (3D) integration of ferroelectric memory devices.

Main Methods:

• Application of hafnia-based ferroelectrics and oxide semiconductors.
• Development of a Si-free integration strategy.
• Device simulation to confirm performance and scalability.

Main Results:

• Successfully avoided the formation of detrimental interfacial layers.
• Achieved superior memory performance compared to conventional flash and previous perovskite ferroelectric memories.
• Demonstrated the feasibility of unprecedented Si-free 3D integration of ferroelectric memory.

Conclusions:

• Hafnia-based ferroelectrics offer a viable path for next-generation memory technologies.
• The proposed Si-free 3D integration strategy overcomes critical challenges in ferroelectric memory.
• This approach paves the way for ultrahigh-density 3D memory integration with enhanced performance.