Electrically Tunable Room Temperature Hysteresis Crossover in Underlap MoS₂ Field-Effect Transistors

Clockwise to anticlockwise hysteresis crossover in current-voltage transfer characteristics of field-effect transistors (FETs) with graphene and MoS₂ channels holds significant promise for nonvolatile memory applications. However, such crossovers have been shown to manifest only at high temperature. In this work, for the first time, we demonstrate room temperature hysteresis crossover in few-layer MoS₂ FETs using a gate-drain underlap design to induce a differential response from traps near the MoS₂-HfO₂ channel-gate dielectric interface, also referred to as border traps, to applied gate bias. The appearance of trap-driven anticlockwise hysteresis at high gate voltages in underlap FETs can be unambiguously attributed to the presence of an underlap since transistors with and without the underlap region were fabricated on the same MoS₂ channel flake. The underlap design also enables room temperature tuning of the anticlockwise hysteresis window (by 140×) as well as the crossover gate voltage (by 2.6×) with applied drain bias and underlap length. Comprehensive measurements of the transfer curves in ambient and vacuum conditions at varying sweep rates and temperatures (RT, 45 °C, and 65 °C) help segregate the quantitative contributions of adsorbates, interface traps, and bulk HfO₂ traps to the clockwise and anticlockwise hysteresis.