Electrically Tunable Room Temperature Hysteresis Crossover in Underlap MoS₂ Field-Effect Transistors

Area of Science:

• Materials Science
• Semiconductor Physics
• Nanotechnology

Background:

• Hysteresis crossover in field-effect transistors (FETs) is crucial for nonvolatile memory.
• Previous demonstrations required high temperatures, limiting practical applications.
• Understanding trap dynamics at the channel-dielectric interface is key.

Purpose of the Study:

• To demonstrate room temperature hysteresis crossover in MoS₂ FETs.
• To investigate the role of a gate-drain underlap design in achieving this phenomenon.
• To analyze the contributions of various trap types to hysteresis behavior.

Main Methods:

• Fabrication of few-layer MoS₂ FETs with and without a gate-drain underlap.
• Characterization of current-voltage transfer characteristics under varying conditions (temperature, sweep rate, ambient/vacuum).
• Analysis of hysteresis behavior to differentiate contributions from border traps, adsorbates, and bulk traps.

Main Results:

• Achieved room temperature clockwise to anticlockwise hysteresis crossover in MoS₂ FETs using an underlap design.
• Demonstrated that the underlap induces differential trap response, enabling anticlockwise hysteresis.
• Showcased room temperature tunability of hysteresis window (140×) and crossover voltage (2.6×) via drain bias and underlap length.
• Quantitatively segregated contributions of adsorbates, interface traps, and bulk HfO₂ traps.

Conclusions:

• The gate-drain underlap design is effective in achieving room temperature hysteresis crossover in MoS₂ FETs.
• This approach offers a pathway for developing practical nonvolatile memory devices operating at ambient temperatures.
• The study provides insights into trap-related hysteresis mechanisms in 2D material-based transistors.