Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs.

Area of Science:

• Computer Engineering
• Hardware Acceleration
• Deep Learning

Background:

• Convolutional Neural Networks (CNNs) are rapidly evolving, necessitating efficient hardware accelerators for real-time applications.
• Field-Programmable Gate Arrays (FPGAs) offer a compelling platform for CNN acceleration due to their reconfigurability, energy efficiency, and low-latency processing capabilities.

Purpose of the Study:

• To introduce a highly customized streaming hardware architecture for full-stack CNN acceleration on FPGAs.
• To enhance compute efficiency for streaming applications by optimizing CNN inference.

Main Methods:

• Developed a unified hardware module for convolutional and deconvolutional layers, efficiently handling residual and concatenative connections.
• Optimized the architecture using multi-level parallelism, layer fusion, and digital signal processing (DSP) blocks.
• Implemented and evaluated the accelerator on Intel's Arria 10 GX1150 FPGA using diverse benchmark models.

Main Results:

• Achieved a high performance exceeding 1.3 TOP/s throughput.
• Demonstrated up to 97% compute (multiply-accumulate, MAC) efficiency.
• Outperformed existing state-of-the-art FPGA accelerators in performance metrics.

Conclusions:

• The proposed streaming hardware architecture effectively accelerates mainstream CNNs with varying topologies on FPGAs.
• This approach significantly improves inference latency and energy efficiency for real-time deployment.
• The architecture represents a significant advancement in FPGA-based CNN acceleration.