Related Experiment Video

Updated: Nov 16, 2025

Optimized Fabrication Procedure for High-Quality Graphene-based Moiré Superlattice Devices
11:24

Optimized Fabrication Procedure for High-Quality Graphene-based Moiré Superlattice Devices

Published on: July 11, 2025

11.1K

Retraction Note: Large-Area Semiconducting Graphene Nanomesh Tailored by Interferometric Lithography

Alireza Kazemi1, Xiang He1, Seyedhamidreza Alaie1,2

  • 1Center for High Technology Materials, University of New Mexico, Albuquerque, NM, 87106, USA.

Scientific Reports
|February 23, 2021
PubMed
Summary

No abstract available in PubMed .

More Related Videos

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities11:42

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

Published on: July 24, 2015

15.8K
Fabricating Nanogaps by Nanoskiving07:36

Fabricating Nanogaps by Nanoskiving

Published on: May 13, 2013

11.4K

Related Concept Videos