A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Area of Science:

• Computer Engineering
• Computer Architecture
• Network-on-Chip Technology

Background:

• Many-Core Systems-on-Chip (SoCs) utilize Networks-on-Chip (NoCs) for scalable connectivity.
• Traditional NoCs face performance limitations due to fixed interconnections that do not adapt to diverse application requirements.
• Software-Defined Networking (SDN) principles are being adopted to create adaptable NoC solutions, termed Software-Defined Network-on-Chip (SDNoC).

Purpose of the Study:

• To explore and classify existing Software-Defined Network-on-Chip (SDNoC) literature based on Software-Defined Networking (SDN) features.
• To identify challenges and opportunities within the current SDNoC research landscape.
• To highlight the need for a complete, layered SDNoC architecture for enhanced Many-Core SoC performance.

Main Methods:

• Literature survey and classification of SDNoC approaches.
• Analysis of implemented SDN features in existing SDNoC designs.
• Comparative study of SDNoC concepts and architectures against traditional NoCs and SDN principles.

Main Results:

• Existing SDNoC works implement only partial Software-Defined Networking (SDN) layered architectures.
• A gap exists in the literature regarding the full adoption of the SDN layered model in Network-on-Chip (NoC) designs.
• The study identifies specific areas within SDNoC architecture where further research and development are needed.

Conclusions:

• Current Software-Defined Network-on-Chip (SDNoC) implementations are incomplete, lacking the full benefits of a layered Software-Defined Networking (SDN) architecture.
• There are significant opportunities for researchers to contribute to the development of more comprehensive and effective SDNoC architectures.
• Advancing SDNoC designs is crucial for optimizing the performance of Many-Core Systems-on-Chip (SoCs).