HBM Connect: High-Performance HLS Interconnect for FPGA HBM.

Area of Science:

• Computer Engineering
• Hardware Acceleration
• Memory Systems

Background:

• High Bandwidth Memory (HBM) based FPGA boards provide unprecedented external memory bandwidth.
• Memory-bound applications can benefit from FPGA acceleration, but efficient utilization remains a challenge.
• Existing High-Level Synthesis (HLS) environments struggle to create efficient communication architectures for multi-channel HBM access, leading to bandwidth degradation.

Purpose of the Study:

• To address the limitations in HBM bandwidth utilization on FPGAs.
• To propose a high-performance customized interconnect, HBM Connect, for FPGA HBM boards.
• To enhance the communication architecture for memory-bound FPGA applications.

Main Methods:

• Development of HBM Connect, a customized interconnect for FPGA HBM boards.
• Introduction of novel HLS-based optimization techniques to improve AXI bus master and switching element throughput.
• Design and integration of a high-performance customized crossbar to potentially replace built-in solutions.

Main Results:

• Demonstration of HBM Connect's effectiveness on the Xilinx Alveo U280 HBM board.
• Case studies using bucket sort and merge sort to explore design spaces and identify optimal resource-performance trade-offs.
• Significant improvements in resource-performance metrics, ranging from 6.5X to 211X, attributed to HBM Connect.

Conclusions:

• HBM Connect effectively overcomes the bandwidth limitations of existing HLS environments for FPGA HBM applications.
• The proposed interconnect and optimization techniques enable fuller exploitation of HBM bandwidth.
• HBM Connect offers substantial performance gains, making FPGA acceleration more viable for memory-intensive tasks.