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Related Concept Videos

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Synaptic integration mainly includes the summation of graded potentials. Graded potentials, regardless of their type, cause subtle alterations in membrane voltage, resulting in either depolarization or hyperpolarization. These incremental changes, when combined or summed, can propel the neuron toward its threshold. Consider, for example, a membrane experiencing a +15 mV shift, causing it to depolarize from -70 mV to -55 mV. In this scenario, graded potentials govern the membrane's ability to...
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Biasing a Junction Field Effect Transistor (JFET) is crucial for setting operational parameters and ensuring efficient functioning in electronic circuits. JFETs are characterized by using a single carrier type in N-channel or P-channel configurations, where the channel is surrounded by PN junctions. These junctions are central to the device's ability to control current flow.
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Real-time Electrophysiology: Using Closed-loop Protocols to Probe Neuronal Dynamics and Beyond
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Integrate-and-Fire Neuron Circuit Without External Bias Voltages.

Young-Soo Park1, Sola Woo1, Doohyeok Lim1

  • 1Department of Electrical Engineering, Korea University, Seoul, South Korea.

Frontiers in Neuroscience
|April 12, 2021
PubMed
Summary

This study introduces a novel integrate-and-fire (I&F) neuron circuit using a p-n-p-n diode. This low-power circuit operates without external bias, achieving high energy efficiency for neuromorphic computing applications.

Keywords:
absence of external bias linesintegrate-and-fire neuronlatch-up phenomenonp-n-p-n diodespiking neural networkstechnology computer-aided design simulation

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Area of Science:

  • Neuromorphic Engineering
  • Solid-State Electronics
  • Computational Neuroscience

Background:

  • Traditional neuron circuits often require complex structures and external bias voltages.
  • Energy efficiency is a critical challenge in scaling neuromorphic computing systems.
  • Latch-up phenomena in semiconductor devices offer potential for novel circuit designs.

Purpose of the Study:

  • To propose and investigate an integrate-and-fire (I&F) neuron circuit utilizing a p-n-p-n diode.
  • To demonstrate I&F operation without external bias voltages.
  • To evaluate the energy efficiency and performance of the proposed circuit.

Main Methods:

  • Mixed-mode Technology Computer-Aided Design (TCAD) simulations were employed.
  • A neuron circuit comprising a p-n-p-n diode, three MOSFETs, and a capacitor was designed.
  • The circuit's operation and energy consumption per spike were analyzed.

Main Results:

  • The proposed I&F neuron circuit operates without external bias lines.
  • Achieved an energy consumption of 0.59 fJ and an energy efficiency of 96.3% per spike.
  • Demonstrated superior structural simplicity and energy efficiency compared to MOSFET-only circuits.

Conclusions:

  • The p-n-p-n diode-based I&F neuron circuit offers a highly energy-efficient and structurally simple solution.
  • The circuit allows for control of firing frequency via synaptic pulse characteristics without external bias.
  • This design presents a promising advancement for low-power neuromorphic hardware.