Interlayer exchange couple based reliable and robust 3-input adder design methodology.

Area of Science:

• Spintronics
• Nanomagnetism
• Device Physics

Background:

• Traditional CMOS technology faces limitations in scaling and power efficiency.
• Dipole coupled nanomagnetic logic (NML) devices struggle with stability at smaller scales and higher temperatures.
• There is a need for robust and energy-efficient logic devices beyond CMOS.

Purpose of the Study:

• To propose and implement a novel inter-layer exchange coupled (IEC) based 3-input full adder.
• To analyze the impact of temperature on the performance and stability of the IEC based full adder.
• To compare the IEC based design with traditional dipole coupled designs.

Main Methods:

• Design and simulation of a 3-input full adder using inter-layer exchange coupling (IEC).
• Implementation and analysis on the micromagnetic Object Oriented MicroMagnetic Framework (OOMMF) platform.
• Temperature-dependent analysis up to the Curie temperature.

Main Results:

• The IEC based full adder operates reliably at sub-50 nm dimensions, even up to the Curie temperature.
• Dipole coupled designs failed at 5 K for sub-50 nm, highlighting IEC's superior thermal stability.
• IEC based designs exhibit lower energy states and greater thermodynamic stability compared to dipole coupled designs.
• Increased temperature led to increased total energy and reduced stability in IEC designs.

Conclusions:

• The IEC architecture offers superior reliability and strength for nanomagnetic logic (NML) devices.
• IEC based designs are a promising pathway towards beyond CMOS computing.
• The proposed IEC full adder design demonstrates significant advantages over dipole coupled counterparts.