A 6.78 MHz, 95.0% Peak Efficiency Monolithic Two-Dimensional Calibrated Active Rectifier for Wirelessly Powered...

Area of Science:

• Electrical Engineering
• Integrated Circuit Design
• Power Electronics

Background:

• Conventional active rectifiers struggle with efficiency when load conditions vary.
• Existing designs often fix power switch size, limiting adaptability.
• Gate transition timing calibration alone is insufficient for wide-ranging load conditions.

Purpose of the Study:

• To propose a fully integrated active rectifier with enhanced power conversion efficiency (PCE).
• To achieve high PCE over a wide loading range by calibrating gate transition timing and power switch size.
• To ensure stable operation of feedback loops under dynamic loading conditions.

Main Methods:

• Implemented a hybrid delay-based gate control circuit (HDGCC) with hybrid feedback loops for on/off transitions.
• Introduced an automatic size selector with a third feedback loop to adjust power switch size dynamically.
• Fabricated the active rectifier using a standard 0.18 μm CMOS process.

Main Results:

• Achieved peak voltage conversion ratio of 97.6% and peak PCE of 95.0% at R_L = 500 Ω.
• Verified effectiveness and robustness through measurements under AC input voltages from 2.5 to 5.0 V.
• Demonstrated stable operation and maintained low voltage drop across NMOS switches.

Conclusions:

• The proposed triple feedback loop active rectifier significantly enhances PCE over a wide loading range.
• Dynamic calibration of both gate transition timing and power switch size is crucial for optimal performance.
• The design offers a robust solution for efficient power conversion in varying load environments.