A Latency-Optimized Network-on-Chip with Rapid Bypass Channels.

Area of Science:

• Computer Engineering
• VLSI Design
• Computer Architecture

Background:

• Network-on-Chips (NoCs) are crucial for scalable, high-bandwidth on-chip communication.
• Increasing node counts in NoCs lead to significant transmission latency.
• Existing solutions like SMART (single-cycle multi-hop asynchronous repeated traversal) introduce overhead.

Purpose of the Study:

• To propose a novel NoC architecture that minimizes transmission latency.
• To reduce the wire overhead associated with bypass mechanisms in NoCs.
• To enhance the efficiency of on-chip communication.

Main Methods:

• Developed a NoC featuring rapid bypass channels.
• Integrated bypass request information directly into each data flit.
• Employed a unicast approach for bypass requests, unlike SMART's broadcast.
• Evaluated performance using four synthetic traffic patterns.

Main Results:

• Achieved a 63.54% reduction in latency compared to a 1-cycle NoC.
• Reduced transmission latency by integrating bypass information with flits.
• Decreased wire overhead by over 80% compared to the SMART NoC.
• Reduced latency by 27% compared to the SMART NoC.

Conclusions:

• The proposed NoC design effectively reduces transmission latency and wire overhead.
• Integrating bypass information into flits offers a more efficient communication method.
• The unicast bypass request mechanism significantly lowers hardware complexity and power consumption.