Jove
Visualize
Contact Us
JoVE
x logofacebook logolinkedin logoyoutube logo
ABOUT JoVE
OverviewLeadershipBlogJoVE Help Center
AUTHORS
Publishing ProcessEditorial BoardScope & PoliciesPeer ReviewFAQSubmit
LIBRARIANS
TestimonialsSubscriptionsAccessResourcesLibrary Advisory BoardFAQ
RESEARCH
JoVE JournalMethods CollectionsJoVE Encyclopedia of ExperimentsArchive
EDUCATION
JoVE CoreJoVE BusinessJoVE Science EducationJoVE Lab ManualFaculty Resource CenterFaculty Site
Terms & Conditions of Use
Privacy Policy
Policies

Related Concept Videos

MOS Capacitor01:25

MOS Capacitor

1.1K
A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...
1.1K
Semiconductors01:22

Semiconductors

1.0K
There is variation in the electrical conductivity of materials - metals, semiconductors, and insulators that are showcased with the help of the energy band diagrams.
Metals such as copper (Cu), zinc (Zn), or lead (Pb) have low resistivity and feature conduction bands that are either not fully occupied or overlap with the valence band, making a bandgap non-existent. This allows electrons in the highest energy levels of the valence band to easily transition to the conduction band upon gaining...
1.0K
Types of Semiconductors01:20

Types of Semiconductors

1.0K
Intrinsic semiconductors are highly pure materials with no impurities. At absolute zero, these semiconductors behave as perfect insulators because all the valence electrons are bound, and the conduction band is empty, disallowing electrical conduction. The Fermi level is a concept used to describe the probability of occupancy of energy levels by electrons at thermal equilibrium. In intrinsic semiconductors, the Fermi level is positioned at the midpoint of the energy gap at absolute zero. When...
1.0K
Ampere-Maxwell's Law: Problem-Solving01:17

Ampere-Maxwell's Law: Problem-Solving

857
A parallel-plate capacitor with capacitance C, whose plates have area A and separation distance d, is connected to a resistor R and a battery of voltage V. The current starts to flow at t = 0. What is the displacement current between the capacitor plates at time t? From the properties of the capacitor, what is the corresponding real current?
To solve the problem, we can use the equations from the analysis of an RC circuit and Maxwell's version of Ampère's law.
For the first part of the...
857
Design Example: Capacitance Multiplier Circuit01:20

Design Example: Capacitance Multiplier Circuit

1.1K
In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
1.1K
Biasing of Metal-Semiconductor Junctions01:27

Biasing of Metal-Semiconductor Junctions

404
Biasing metal-semiconductor junctions involves applying a voltage across the junction. Specifically, the metal is connected to a voltage source, while the semiconductor is grounded. This technique is essential for controlling the direction and magnitude of current flow in electronic devices, including diodes, transistors, and photovoltaic cells.
In Schottky junctions, where the semiconductor is n-type, applying a positive voltage to the metal relative to the semiconductor reduces its Fermi...
404

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by
Same author

Reconfigurable Photoelectric Coaxial Fiber-Based Memristors for Neuromorphic Computing.

ACS nano·2026
Same author

Influence of Device Structure and Manufacturing Thermal Budget on Channel Release Module in GAA NSFET and Process Optimization.

Nanomaterials (Basel, Switzerland)·2026
Same author

Genomic features do not account for differences in multiple myeloma risk by ancestry.

Blood cancer discovery·2026
Same author

Leucyl tRNA synthetase ameliorates cholestatic liver injury by inhibiting integrated stress response in mice.

Scientific reports·2026
Same author

The Formation Mechanism and Regulation of Fermented Bean Paste Flavor: Microbial Community Succession, Flavor Compound Synthesis, and Applications of Intelligent Biomanufacturing Technology.

Comprehensive reviews in food science and food safety·2026
Same author

Monolithic integration of p- and n-type doped 2D WSe<sub>2</sub> for wafer-scale complementary logic circuits.

Nature communications·2026

Related Experiment Video

Updated: Nov 2, 2025

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform
05:39

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Published on: August 2, 2019

9.9K

An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations.

Yin Wang1, Hongwei Tang1, Yufeng Xie1

  • 1State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China.

Nature Communications
|June 8, 2021
PubMed
Summary
This summary is machine-generated.

This study introduces a novel circuit using molybdenum disulfide (MoS2) transistors for efficient in-memory computing. The design enables high-capacity multiply-accumulate operations crucial for artificial intelligence (AI) hardware.

More Related Videos

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
07:12

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Published on: August 28, 2018

9.9K
Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes
08:07

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Published on: March 9, 2019

8.1K

Related Experiment Videos

Last Updated: Nov 2, 2025

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform
05:39

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Published on: August 2, 2019

9.9K
A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
07:12

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

Published on: August 28, 2018

9.9K
Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes
08:07

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Published on: March 9, 2019

8.1K

Area of Science:

  • Materials Science
  • Electrical Engineering
  • Computer Science

Background:

  • Multiply-accumulate (MAC) operations are fundamental to artificial intelligence (AI) but face challenges in energy efficiency and miniaturization.
  • In-memory computing offers a promising approach to overcome the von Neumann bottleneck by performing computations within memory.

Purpose of the Study:

  • To propose and evaluate a novel circuit architecture for efficient in-memory computing using monolayer MoS2 transistors.
  • To demonstrate the feasibility of integrating MAC operations into a compact, energy-efficient hardware design.

Main Methods:

  • A two-transistor-one-capacitor (2T-1C) circuit architecture was designed, integrating monolayer MoS2 transistors.
  • The circuit leverages the properties of MoS2 transistors for analog computation and multi-level voltage storage.
  • A neural network was trained ex-situ using the developed circuit for image recognition tasks.

Main Results:

  • The proposed 2T-1C circuit architecture enables efficient MAC operations with characteristics similar to Dynamic Random Access Memory (DRAM).
  • Ultralow leakage current in MoS2 transistors allows for long data retention and multi-level voltage storage.
  • An ex-situ trained neural network achieved 90.3% accuracy in image recognition, validating the circuit's performance.

Conclusions:

  • The developed MoS2-based 2T-1C circuit offers a viable solution for high-capacity, energy-efficient in-memory computing.
  • Future integration into 3D circuits could enable low-power, in-situ training of neural networks directly in hardware.