Influence of Device Structure and Manufacturing Thermal Budget on Channel Release Module in GAA NSFET and Process...

Area of Science:

• Semiconductor device physics and manufacturing
• Advanced materials for microelectronics
• Nanoscale fabrication technologies

Background:

• Gate-all-around nanosheet field-effect transistors (GAA NSFETs) represent the next generation of logic device architecture.
• The channel release process is critical for GAA NSFET performance, impacting turn-on voltage and operating speed.
• Existing manufacturing methods face challenges due to complex structures and thermal budgets in GAA NSFETs.

Purpose of the Study:

• To investigate the application of non-plasma gas etching for the channel release process in GAA NSFETs.
• To systematically analyze the effects of process parameters on etching quality.
• To optimize the channel release process for high selectivity and minimal damage.

Main Methods:

• Utilized non-plasma gas etching for SiGe/Si channel release in GAA NSFET fabrication.
• Systematically varied nanosheet width, spacing, and annealing conditions.
• Investigated the impact of *H radical pretreatment on channel surface roughness.

Main Results:

• Achieved a high SiGe/Si etching selectivity of 87.
• Demonstrated that increasing channel width reduces single-sided damage in Si nanosheets.
• Controlled Si single-sided damage below 1 nm even with >100% over-etching.
• Observed intensified Ge diffusion and slowed SiGe etching with increased annealing temperature.
• Reduced channel surface roughness (RMS) from 0.087 to 0.069 nm using *H radical pretreatment.

Conclusions:

• Non-plasma gas etching offers a viable, low-damage, high-selectivity solution for GAA NSFET channel release.
• Process parameter control, including width, spacing, and annealing, is crucial for optimizing etching.
• *H radical pretreatment effectively improves channel surface quality.