Ternary logic decoder using independently controlled double-gate Si-NW MOSFETs.

Area of Science:

• Semiconductor device physics
• Nanoelectronics
• Digital logic design

Background:

• Ternary logic decoders (TLDs) are crucial for mixed radix systems (MRS).
• Conventional multi-threshold voltage (multi-Vth) schemes present limitations for TLD implementation.
• Silicon-nanowire (Si-NW) field-effect transistors (FETs) offer potential for advanced logic circuits.

Purpose of the Study:

• To demonstrate a ternary logic decoder (TLD) using independently controlled double-gate (ICDG) silicon-nanowire (Si-NW) MOSFETs.
• To confirm the feasibility of mixed radix systems (MRS) employing this novel TLD design.
• To resolve limitations associated with conventional multi-threshold voltage (multi-Vth) schemes in TLDs.

Main Methods:

• Fabrication and characterization of ICDG Si-NW MOSFETs.
• Semi-empirical modeling and fitting of electrical characteristics using SILVACO ATLAS TCAD simulator.
• Mixed-mode TCAD simulations to analyze TLD circuit performance and power consumption.

Main Results:

• The ICDG Si-NW MOSFETs were successfully fabricated and characterized.
• Electrical characteristics were accurately modeled and fitted.
• The TLD achieved a power-delay product of 35 aJ for a 500 nm gate length and 0.16 aJ for a 14 nm gate length.

Conclusions:

• The demonstrated TLD based on ICDG Si-NW MOSFETs is a feasible component for mixed radix systems.
• This approach overcomes limitations of conventional multi-Vth schemes.
• The CMOS-compatible and scalable nature of these MOSFETs makes them promising for future ternary and binary logic MRS.