Related Experiment Video
Updated: Nov 1, 2025

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating
Published on: April 12, 2018
Ultrafast switching and linear conductance modulation in ferroelectric tunnel junctions via P(VDF-TrFE) morphology
1VTT Technical Research Centre of Finland Ltd., P.O. Box 1000, FI-02044 VTT, Finland. sayani.majumdar@vtt.fi.
Abstract:
Neuromorphic computing architectures demand the development of analog, non-volatile memory components operating at femto-Joule/bit operation energy. Electronic components working in this energy range require devices operating at ultrafast timescales. Among different non-volatile, analog memories, ferroelectric tunnel junctions (FTJs) have emerged as an important contender due to their voltage-driven operation leading to extreme energy-efficiency. Here, we report a study on the switching timescale and linear conductance modulation of organic FTJs comprising a metal/ferroelectric/semiconductor (MFS) stack with different morphologies of ferroelectric copolymer P(VDF-TrFE) ultrathin films. The results show that due to different annealing temperatures and protocols, the spin-coated copolymer films are modified significantly, which can have a large effect on the switching timescales and threshold fields of the FTJs with the best quality devices having a projected switching timescale of sub-nanosecond range. An improvement in switching speed by 7 orders of magnitude can be obtained with an increase of the programming voltage by less than a factor of 2 in these devices. This ultrafast switching of ferroelectric domains in our FTJs leads to pico to femto joule range of operation energy per bit opening the pathways for energy efficient and fast operating non-volatile memories while devices with higher domain pinning sites show a route for tuning analog conductivity for bio-realistic neuromorphic architectures.
More Related Videos
10:40A Fabrication and Measurement Method for a Flexible Ferroelectric Element Based on Van Der Waals Heteroepitaxy
Published on: April 8, 2018
11:33All-electronic Nanosecond-resolved Scanning Tunneling Microscopy: Facilitating the Investigation of Single Dopant Charge Dynamics
Published on: January 19, 2018
Related Concept Videos
Biasing of FET
In an N-channel JFET, the structure consists of N-type material forming the channel on a P-type substrate, with the...
Field Effect Transistor
MOSFET: Enhancement Mode
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...
Characteristics of JFET
The core of a JFET's operation is controlling drain current by modulating the gate-source voltage. When the drain and gate voltage are set to zero, the JFET exhibits no net current flow, representing a state of equilibrium. The drain current increases linearly as the...
Biasing of Metal-Semiconductor Junctions
In Schottky junctions, where the semiconductor is n-type, applying a positive voltage to the metal relative to the semiconductor reduces its Fermi...
Biasing of P-N Junction
In equilibrium, no external voltage is applied across the p-n junction. The depletion region is formed at the junction interface due to the diffusion of carriers, which leaves behind charged dopants, acceptors on the p-side, and donors on the n-side. These immobile charges create an electric field that prevents further diffusion of carriers. The related energy band...