On-chip integrated Si-tip field electron emission vacuum transistor with saturated output characteristics

On-chip integrated field-emission vacuum transistors (FEVTs) have attracted significant interest owing to their potential robustness in harsh environments. However, their miniaturization involves a fundamental trade-off. Specifically, a narrower cathode-anode separation lowers the operating voltage but allows the anode electric field to influence the cathode surface barrier, thereby hindering output current saturation. A narrower cathode-gate separation enhances gate control but increases electron interception at the gate, which degrades anode collection efficiency and limits the output current. In this work, we demonstrate an on-chip integrated vertical Si-tip FEVT that alleviates this trade-off via a synergistic structural design. The design synergistically optimizes the gate height, gate aperture radius, and anode aperture radius to shield the cathode from the anode field. Simultaneously, an integrated ultra-sharp Si tip provides highly collimated electron emission, which mitigates electron interception by the gate and thereby maintains an anode collection efficiency above 80%. The optimized single Si-tip FEVT exhibits clear current saturation, achieves an on/off ratio of 9.6 × 10⁴, and delivers an anode current of 1.24 μA at a gate voltage of 100 V. Furthermore, a 40 × 40 Si-tip array FEVT leverages current superposition from multiple tips to achieve enhanced performance. The array delivers 1.24 μA (comparable to the single-tip device) at a gate voltage of only 50 V, and reaches 7.57 μA with an on/off ratio of 1.06 × 10⁶ at a gate voltage of 80 V. This work provides a design strategy for linear-mode vacuum microelectronic devices.