NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark.

Area of Science:

• Computer Engineering
• Hardware Accelerators
• Memory Technologies

Background:

• Deep neural networks (DNNs) require efficient processing of multiply-and-accumulate (MAC) operations.
• Compute-in-memory (CIM) architectures offer a promising solution for DNN hardware accelerators.
• Early-stage design space exploration necessitates accurate simulation tools for CIM.

Purpose of the Study:

• To validate and calibrate the DNN+NeuroSim framework against RRAM-based CIM macro post-layout simulations.
• To assess the accuracy of NeuroSim predictions for CIM hardware accelerators.
• To enable reliable early-stage design exploration of CIM accelerators.

Main Methods:

• Extracted device and transistor parameters from foundry Process Design Kits (PDKs) for NeuroSim configuration.
• Matched peripheral modules and operating dataflow to actual chip implementation.
• Compared SPICE simulation results (area, critical path, energy) with NeuroSim predictions, introducing adjustment factors for layout effects.

Main Results:

• Achieved precise NeuroSim predictions with less than 1% chip-level error after calibration.
• Validated that general system-level performance conclusions remain consistent post-calibration.
• Observed a slight performance degradation due to post-layout calibration, attributed to factors like transistor sizing and wiring.

Conclusions:

• The calibrated DNN+NeuroSim framework provides accurate predictions for RRAM-based CIM hardware accelerators.
• NeuroSim is a reliable tool for efficient early-stage design space exploration of CIM accelerators.
• Post-layout effects necessitate calibration for precise CIM hardware accelerator performance estimation.