Efficient FPGA Implementation of a Dual-Frequency GNSS Receiver with Robust Inter-Frequency Aiding.

Area of Science:

• Electrical Engineering
• Signal Processing
• Satellite Navigation

Background:

• Multiple frequency Global Navigation Satellite System (GNSS) receivers face complexity with additional channels.
• Existing auxiliary methods for synchronizing secondary GNSS signals are limited by reception uncertainties (noise, interference).
• Signal uncertainties can disrupt the relationship between dual-frequency Doppler frequencies.

Purpose of the Study:

• To implement an efficient dual-frequency Field-Programmable Gate Array (FPGA) based GNSS receiver.
• To develop a direct aid tracking method for secondary channels, enhancing resource efficiency and robustness.
• To propose a robust estimator that directly links tracking loops in dual-frequency bands.

Main Methods:

• Development of a robust estimator designed to handle signal uncertainties.
• Implementation of a primary tracking scheme to establish error boundaries.
• Utilizing a tracked bit-boundary for the initial code phase of the secondary channel.

Main Results:

• Successful implementation of direct aid tracking for dual-frequency GNSS signals on an FPGA.
• Demonstration of a robust channel link capable of direct aid tracking.
• Achieved a satisfactory release of 31.02% of hardware resources from the aided acquisition module.

Conclusions:

• The proposed robust estimator and direct aid tracking method significantly improve resource efficiency in dual-frequency GNSS receivers.
• The FPGA implementation provides a robust solution for GNSS signal synchronization despite reception uncertainties.
• This approach offers a more reliable and resource-efficient alternative for advanced GNSS applications.