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MOS Capacitor

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A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
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Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

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Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications.

Md Hasan Raza Ansari¹, Udaya Mohanan Kannan¹, Seongjae Cho¹

¹Graduate School of IT Convergence Engineering, Gachon University, Seongnam 13120, Korea.

Nanomaterials (Basel, Switzerland)

|August 7, 2021

Summary

This study introduces a core-shell dual-gate nanowire transistor as an artificial synapse. It demonstrates short-term and long-term memory functions, achieving high accuracy in pattern recognition for neuromorphic hardware applications.

Keywords:

band-to-band tunneling charge-trap synaptic transistor long-term potentiation (LTP)neural network neuromorphic system pattern recognition short-term potentiation (STP)

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Area of Science:

* Materials Science and Engineering
* Electrical Engineering
* Neuroscience

Background:

* Artificial synaptic devices are crucial for developing brain-inspired computing.
* Existing devices face challenges in mimicking neural plasticity like short-term potentiation (STP) and long-term potentiation (LTP).
* Long-term depression (LTD) is another key synaptic function requiring efficient implementation.

Purpose of the Study:

* To investigate the physical mechanisms of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device.
* To demonstrate the transistor's capability for STP, LTP, and LTD operations.
* To evaluate the device's performance in pattern recognition tasks and its suitability for neuromorphic hardware.

Main Methods:

* Utilizing floating body effects and charge trapping within the nanowire transistor to achieve STP and LTP.
* Employing de-trapping of holes from the nitride layer to exhibit LTD operation.
* Optimizing device design and applied biases for linear and symmetric conductance characteristics.

Main Results:

* Successfully demonstrated the transition from STP to LTP through controlled charge trapping and de-trapping mechanisms.
* Achieved linearity and symmetry in synaptic conductance, crucial for reliable operation.
* Attained a recognition accuracy of up to 92.28% in Modified National Institute of Standards and Technology (MNIST) pattern recognition tasks via system-level simulation.

Conclusions:

* The CSDG nanowire transistor effectively emulates synaptic functions, including short-term and long-term plasticity.
* Optimal device design and bias conditions ensure reliable and symmetric synaptic weight modulation.
* High recognition accuracy and CMOS compatibility position the CSDG nanowire transistor as a strong candidate for next-generation neuromorphic computing hardware.