Search research articles

ABOUT JoVE

Overview Leadership Blog JoVE Help Center

AUTHORS

Publishing Process Editorial Board Scope & Policies Peer Review FAQ Submit

LIBRARIANS

Testimonials Subscriptions Access Resources Library Advisory Board FAQ

RESEARCH

JoVE Journal Methods Collections JoVE Encyclopedia of Experiments Archive

EDUCATION

JoVE Core JoVE Business JoVE Science Education JoVE Lab Manual Faculty Resource Center Faculty Site

Terms & Conditions of Use

Related Concept Videos

Design Example: Capacitance Multiplier Circuit

Design Example: Capacitance Multiplier Circuit

In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.

Convolution: Math, Graphics, and Discrete Signals

Convolution: Math, Graphics, and Discrete Signals

In any LTI (Linear Time-Invariant) system, the convolution of two signals is denoted using a convolution operator, assuming all initial conditions are zero. The convolution integral can be divided into two parts: the zero-input or natural response and the zero-state or forced response, with t0 indicating the initial time.
To simplify the convolution integral, it is assumed that both the input signal and impulse response are zero for negative time values. The graphical convolution process...

Ampere-Maxwell's Law: Problem-Solving

Ampere-Maxwell's Law: Problem-Solving

A parallel-plate capacitor with capacitance C, whose plates have area A and separation distance d, is connected to a resistor R and a battery of voltage V. The current starts to flow at t = 0. What is the displacement current between the capacitor plates at time t? From the properties of the capacitor, what is the corresponding real current?
To solve the problem, we can use the equations from the analysis of an RC circuit and Maxwell's version of Ampère's law.
For the first part of...

Parallel Processing

Parallel Processing

The brain processes sensory information rapidly due to parallel processing, which involves sending data across multiple neural pathways at the same time. This method allows the brain to manage various sensory qualities, such as shapes, colors, movements, and locations, all concurrently. For instance, when observing a forest landscape, the brain simultaneously processes the movement of leaves, the shapes of trees, the depth between them, and the various shades of green. This enables a quick and...

Fast Decoupled and DC Powerflow

Fast Decoupled and DC Powerflow

The fast decoupled power flow method addresses contingencies in power system operations, such as generator outages or transmission line failures. This method provides quick power flow solutions, essential for real-time system adjustments. Fast decoupled power flow algorithms simplify the Jacobian matrix by neglecting certain elements, leading to two sets of decoupled equations:

Convolution Properties II

Convolution Properties II

The important convolution properties include width, area, differentiation, and integration properties.
The width property indicates that if the durations of input signals are T1 and T2, then the width of the output response equals the sum of both durations, irrespective of the shapes of the two functions. For instance, convolving two rectangular pulses with durations of 2 seconds and 1 second results in a function with a width of 3 seconds.
The area property asserts that the area under the...

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by

Same author

Spare-Row-Based Fault-Tolerant Dynamic Operation Units for RRAM Computing-in-Memory Systems.

Micromachines·2026

Same author

Block-Based Compression and Corresponding Hardware Circuits for Sparse Activations.

Sensors (Basel, Switzerland)·2021

See all related articles

Search research articles

Related Experiment Video

Updated: Oct 25, 2025

Design and Analysis for Fall Detection System Simplification

Design and Analysis for Fall Detection System Simplification

Published on: April 6, 2020

Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing.

Hsu-Yu Kao¹, Xin-Jia Chen¹, Shih-Hsu Huang¹

¹Department of Electronic Engineering, Chung Yuan Christian University, Taoyuan 32023, Taiwan.

Sensors (Basel, Switzerland)

|August 10, 2021

Summary

This summary is machine-generated.

This study introduces a novel low-power signed convolver hardware architecture for edge computing. The design reduces power consumption by 15.6% and saves a clock cycle per convolution operation.

Keywords:

adder trees convolution operations dataflow digital circuits logic design multiplications partial product reduction

More Related Videos

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Published on: August 2, 2019

Large Scale Energy Efficient Sensor Network Routing Using a Quantum Processor Unit

Large Scale Energy Efficient Sensor Network Routing Using a Quantum Processor Unit

Published on: September 8, 2023

Related Experiment Videos

Last Updated: Oct 25, 2025

Design and Analysis for Fall Detection System Simplification

Design and Analysis for Fall Detection System Simplification

Published on: April 6, 2020

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Published on: August 2, 2019

Large Scale Energy Efficient Sensor Network Routing Using a Quantum Processor Unit

Large Scale Energy Efficient Sensor Network Routing Using a Quantum Processor Unit

Published on: September 8, 2023

Area of Science:

Computer Engineering
Hardware Architecture
Artificial Intelligence

Background:

Convolution operations are critical for convolutional neural network (CNN) performance.
Edge-computing hardware design demands efficient and low-power solutions.

Purpose of the Study:

To propose a low-power signed convolver hardware architecture for edge computing.
To enhance the efficiency and reduce the power consumption of convolution operations in CNNs.

Main Methods:

A novel convolver design combining multipliers' final additions into a partial product matrix (PPM).
Utilizing a reduction tree algorithm to minimize the PPM.
Developing two types of convolve-accumulate units adaptable to various dataflows (input, weight, output stationary).

Main Results:

The proposed convolver design saves carry propagation adders and one clock cycle per convolution.
Achieves a 15.6% reduction in power consumption compared to state-of-the-art approaches.
The convolve-accumulate units reduce power consumption by an average of 15.7%.

Conclusions:

The proposed low-power signed convolver architecture offers significant power savings for edge computing.
The design's adaptability to different dataflows enhances its versatility.
This architecture is well-suited for power-constrained edge AI applications.