An FPGA Based Energy-Efficient Read Mapper With Parallel Filtering and In-Situ Verification.

Area of Science:

• Genomics
• Bioinformatics
• Computer Architecture

Background:

• Whole Genome Sequencing (WGS) read mapping is computationally intensive, requiring significant energy and hardware resources in data centers.
• Current methods for genome re-assembly face challenges due to high setup, energy, and cooling costs.
• Enabling low-cost genomics necessitates energy-efficient computational approaches.

Purpose of the Study:

• To propose an energy-efficient architectural methodology for read mapping on a single System-on-Chip (SoC) platform.
• To reduce the computational and energy costs associated with Whole Genome Sequencing (WGS).
• To enable low-cost genomics through optimized hardware design.

Main Methods:

• Developed a novel SoC architecture for read mapping based on the q-gram lemma.
• Implemented a parallel sorted q-gram lemma for filtering and an in-situ verification routine using the parallel Myers bit-vector algorithm.
• Designed and implemented the methodology on the Zynq Ultrascale+ XCZU9EG MPSoC platform.

Main Results:

• Achieved up to 7.8× energy reduction compared to state-of-the-art approaches.
• Demonstrated up to 13.3× less resource utilization.
• Validated the methodology using real genomic data, confirming significant efficiency gains.

Conclusions:

• The proposed energy-efficient SoC architecture offers a viable solution for low-cost genomics.
• This approach significantly reduces energy consumption and resource utilization in WGS read mapping.
• The novel parallel q-gram and Myers bit-vector algorithms contribute to efficient genome re-assembly.