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Toward Low-Temperature Solid-Source Synthesis of Monolayer MoS2.

Alvin Tang1, Aravindh Kumar1, Marc Jaikissoon1

  • 1Department of Electrical Engineering, Stanford University, Stanford, California 94305, United States.

ACS Applied Materials & Interfaces
|August 24, 2021
PubMed
Summary

Researchers developed a new method for growing 2D molybdenum disulfide (MoS2) films at low temperatures. This breakthrough enables thermal-budget-compatible MoS2 for integration with silicon technology.

Keywords:
2D materialsBEOLCVD growthMoS2back-end-of-the-linecarrier mobilitychemical vapor depositionmolybdenum disulfidetransition metal dichalcogenides

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Area of Science:

  • Materials Science
  • Semiconductor Physics
  • Nanotechnology

Background:

  • Two-dimensional (2D) semiconductors offer potential for heterogeneous integration with silicon.
  • High chemical vapor deposition (CVD) growth temperatures of 2D materials limit compatibility with silicon manufacturing.
  • A need exists for low-temperature synthesis methods for 2D semiconductors.

Purpose of the Study:

  • To demonstrate direct CVD solid-source precursor synthesis of continuous monolayer (1L) MoS2 films.
  • To achieve growth within the thermal budget required for back-end-of-the-line silicon technology compatibility.
  • To evaluate the performance of synthesized MoS2 films in transistors.

Main Methods:

  • Direct CVD solid-source precursor synthesis of MoS2.
  • Growth temperature optimized to 560 °C with a 50 min deposition time.
  • Fabrication and characterization of field-effect transistors (FETs) with 100 nm channel lengths.

Main Results:

  • Continuous monolayer MoS2 films were synthesized at 560 °C within a 2 h thermal budget.
  • Transistors exhibited high on-state current (∼140 μA/μm at 1 V) for 1L MoS2 grown below 600 °C.
  • Effective electron mobility of 29 ± 5 cm2 V-1 s-1 was achieved, comparable to higher-temperature grown films.

Conclusions:

  • Low-temperature CVD synthesis of high-quality MoS2 is feasible.
  • The developed method meets thermal budget requirements for silicon manufacturing integration.
  • This work paves the way for thermal-budget-compatible 2D semiconductors in heterogeneous integration.