Gate-Dielectric Engineering with an Ultrathin Silicon Oxide Interfacial Dipole Layer for Low-Leakage...

We demonstrate a gate-dielectric engineering approach leveraging an ultrathin, atomic-layer-deposited silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL positively shifts the threshold voltage (V_T) of AOS transistors, providing at least four distinct V_T levels with a maximum increase of 500 mV. It achieves stable V_T control without significantly degrading critical device parameters such as mobility and on-state current, all while keeping the process temperature below 225 °C and requiring no additional heat treatment to activate the dipole. Positive-bias temperature instability tests at 85 °C indicate a significant reduction in negative V_T shifts for SiL-integrated devices, highlighting the enhanced reliability. Incorporating this SiL gate stack into two-transistor gain-cell (GC) memory maintains a more stable storage node voltage (V_SN) (reduces V_SN drop by 67%), by limiting unwanted charge losses. SiL-engineered GCs also reach retention times up to 10000 s at room temperature and reduce standby leakage current by 3 orders of magnitude relative to baseline device, substantially lowering refresh energy consumption.