Reversibly Stacked Monolithic 3D Integrated Circuits.

Area of Science:

• Materials Science
• Semiconductor Physics
• Electrical Engineering
• Nanotechnology

Background:

• Monolithic three-dimensional (3D) integration offers high-density, energy-efficient logic and memory systems through vertical device stacking.
• Existing 3D integration methods are limited by a 400°C thermal budget, restricting semiconductor choices and stacking sequences.
• Low-temperature semiconductor research has been hindered by fixed fabrication sequences due to high-temperature processing needs.

Purpose of the Study:

• To demonstrate a monolithic 3D (M3D) complementary field-effect transistor (FET) architecture overcoming thermal constraints.
• To enable flexible, low-temperature fabrication of vertically integrated logic and memory systems.
• To achieve design freedom in stacking sequences for advanced 3D integrated circuits.

Main Methods:

• Utilized low-temperature deposition of n-type Indium Oxide (In2O3) and p-type Tellurium (Te) semiconductors.
• Developed a M3D complementary FET architecture enabling reversed n- and p-type sequences.
• Fabricated CMOS inverters, multilayer logic stacks, and a 3D Static Random-Access Memory (SRAM) cell below 300°C.

Main Results:

• Successfully demonstrated a M3D complementary FET architecture using In2O3 and Te semiconductors below 300°C.
• Achieved design flexibility to reverse n- and p-type semiconductor stacking sequences, overcoming previous thermal limitations.
• Integrated functional CMOS inverters, multilayer logic, and a complete 3D SRAM cell within the low-temperature budget.

Conclusions:

• The developed scalable platform provides a practical pathway for low-temperature, vertically integrated complementary logic.
• This approach enables intrinsic interconnects for advanced 3D system-on-chip (SoC) technologies.
• The demonstrated flexibility in stacking sequences paves the way for next-generation energy-efficient 3D integrated circuits.