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Updated: Aug 27, 2026

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
Published on: August 28, 2018
Deep Learning to Automate Parameter Extraction and Model Fitting of Two-Dimensional Transistors
Robert K A Bennett1, Jan-Lucas Uslu2,3, Harmon F Gault1
1Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA.
Abstract:
We present a deep learning approach to extract physical parameters (e.g., mobility, Schottky contact barrier height, and defect profiles) of two-dimensional (2D) transistors from electrical measurements, enabling automated parameter extraction and technology computer-aided design (TCAD) fitting. To facilitate this task, we implement a simple data augmentation and pretraining approach by training a secondary neural network to approximate a physics-based device simulator. This method enables high-quality fits after training the neural network on electrical data generated from physics-based simulations of ~500 devices, a factor >40× fewer than other recent efforts. Consequently, fitting can be achieved by training on physically rigorous TCAD models, including complex geometry, self-consistent transport, and electrostatic effects, and is not limited to computationally inexpensive compact models. We apply our approach to reverse-engineer key parameters from experimental monolayer WS2 transistors, achieving a median coefficient of determination (R 2) = 0.99 when fitting measured electrical data. We also demonstrate that this approach generalizes and scales well by reverse-engineering electrical data from high-electron-mobility transistors while fitting 35 parameters simultaneously. To facilitate future research on deep learning approaches for the inverse design of transistors, we have published our code and sample datasets online.
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