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Updated: Oct 22, 2025
09:49
In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx
Published on: May 13, 2020
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Induced Complementary Resistive Switching in Forming-Free TiO/TiO2/TiO Memristors
Saurabh Srivastava1,2, Joseph Palathinkal Thomas1, Xiaoyi Guan1
1WATLab and Department of Chemistry, University of Waterloo, 200 University Avenue West, Waterloo, Ontario N2L 3G1, Canada.
ACS Applied Materials & Interfaces
|August 31, 2021
Summary
This study introduces a novel heterojunction design for memristor arrays, effectively suppressing sneak currents. The new double-junction architecture enhances memory integration by preventing half-selected cells and improving data reliability.
Area of Science:
- Materials Science
- Nanotechnology
- Electrical Engineering
Background:
- Sneak current paths pose a significant challenge in high-density cross-bar memristor arrays.
- Existing single-layer structures struggle with undesired half-selected cells, leading to incorrect readouts.
Purpose of the Study:
- To develop a new heterojunction design for oxide multilayer stacking to manipulate oxidation states.
- To transform bipolar resistive switching (BRS) to complementary resistive switching (CRS) in memristor arrays.
- To overcome sneak path constraints in high-density memory integration.
Main Methods:
- Fabrication of a Pt/TiO/TiO2/TiO/Pt double-junction memristor device architecture.
- Manipulation of oxygen vacancy content in oxide layers to control oxidation states.
- Characterization of resistive switching behavior and analysis of sneak current suppression.
Main Results:
- The double-junction architecture exhibits complementary resistive switching (CRS), unlike the single-layer BRS.
- The device maintains a high-resistance state below the SET voltage, effectively eliminating sneak path issues.
- Demonstrated high-quality switching performance with excellent endurance and current retention.
Conclusions:
- The proposed heterojunction design successfully mitigates sneak current problems in memristor arrays.
- This architecture offers a viable solution for reliable high-density memory integration.
- The simplified switching model accurately describes the observed performance characteristics.
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