Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing.

Area of Science:

• Computer Engineering
• Digital Signal Processing
• Embedded Systems

Background:

• Field-Programmable Gate Arrays (FPGAs) offer potential for high-level image processing but are limited by on-chip memory capacity.
• Efficient memory resource utilization is critical for meeting performance, size, and power constraints in FPGA designs.

Purpose of the Study:

• To investigate novel methods for allocating on-chip memory resources in FPGAs to minimize usage and power consumption.
• To enable power-efficient, high-level image processing applications that can be fully implemented on FPGAs.

Main Methods:

• Developed algorithms for generating memory architectures from Hardware Description Languages (HDLs) and High-Level Synthesis (HLS) designs.
• Formalized on-chip memory configuration options and employed a power model to evaluate partitioning strategies.
• Compared proposed algorithms against traditional strategies and commercial FPGA synthesis/HLS tools.

Main Results:

• Achieved up to 60% higher memory utilization efficiency compared to commercial tools, allowing for larger or more image frames.
• Reduced dynamic power consumption of frame buffers by up to approximately 70%.
• Demonstrated significant power reductions (up to 25% for Optical Flow, 30% for MeanShift Tracking) without performance degradation.

Conclusions:

• The proposed memory partitioning algorithms effectively address FPGA on-chip memory limitations for high-level image processing.
• These methods contribute to the development of more power-efficient and capable FPGA-based image processing systems.
• The algorithms offer a superior alternative to traditional strategies for optimizing memory usage and power in FPGA designs.