FTA-GAN: A Computation-Efficient Accelerator for GANs With Fast Transformation Algorithm.

Area of Science:

• Machine Learning
• Computer Architecture
• Deep Learning

Background:

• Generative Adversarial Networks (GANs) are powerful but computationally intensive, particularly due to deconvolution operations.
• Existing hardware accelerators for deconvolution face challenges like computation imbalance and high memory demands, limiting real-time GAN applications.
• There is a need for efficient hardware solutions to overcome the computational bottlenecks in GANs.

Purpose of the Study:

• To develop a novel fast transformation algorithm (FTA) for deconvolution computation.
• To design a computation-efficient hardware architecture for GANs based on the FTA.
• To improve the real-time performance and reduce the resource requirements of GANs.

Main Methods:

• Introduced a novel fast transformation algorithm (FTA) to address computation imbalance and memory issues in deconvolution.
• Developed a fast computing core (FCC) and computing array based on FTA for efficient deconvolution.
• Optimized dataflow and storage schemes for enhanced on-chip memory reuse and computation efficiency.
• Implemented and validated a hardware architecture for GANs on FPGA, testing with DCGAN, EBGAN, and WGAN benchmarks.

Main Results:

• The proposed design achieves 2211 GOPS at 185 MHz on an Intel Stratix 10SX FPGA.
• Demonstrated over 2x hardware efficiency improvement compared to previous deconvolution accelerator designs.
• Significantly reduced storage requirements for GAN computations.
• Achieved satisfactory visual results on various GAN benchmarks.

Conclusions:

• The novel FTA and FCC provide a computation-efficient solution for deconvolution in GANs.
• The proposed hardware architecture significantly enhances GAN performance and reduces resource utilization.
• This work enables more practical and efficient real-time applications of GANs.