A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step...

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Neuroscience

Background:

• Neuromorphic hardware systems are increasingly vital for embedded applications due to their energy efficiency and brain-inspired spiking neural network (SNN) models.
• SNNs mimic the human cortex, processing information via sparse spikes, making them suitable for complex sensory data.

Purpose of the Study:

• To propose a scalable, cost-efficient, and high-speed VLSI architecture for accelerating deep SCNN inference.
• To enable real-time, low-cost embedded applications by optimizing SCNN processing.

Main Methods:

• Leveraging SCNN characteristics by decomposing operations into time-step CNN-like processing using binary spike map snapshots.
• Reducing hardware resource consumption through simplified, regular processing steps.
• Achieving high throughput via a pixel stream processing mechanism and fine-grained data pipelines.

Main Results:

• A Zynq-7045 FPGA prototype demonstrated high processing speeds of 1250 frames/s.
• High recognition accuracies were achieved on the MNIST and Fashion-MNIST image datasets.
• The architecture proved plausible for various embedded applications.

Conclusions:

• The developed VLSI architecture effectively accelerates deep SCNN inference for embedded systems.
• The system offers a scalable, cost-efficient, and high-speed solution for real-time applications.
• The prototype's performance validates the SCNN hardware architecture's potential in embedded scenarios.