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Related Experiment Video

Updated: Oct 18, 2025

Large Scale Energy Efficient Sensor Network Routing Using a Quantum Processor Unit
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Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks.

Sangjun Lee1, Kyunghwan Cho1, Jihye Kim1

  • 1Electrical and Electronic Engineering Department, Yonsei University, Seoul 03722, Korea.

Sensors (Basel, Switzerland)
|September 28, 2021
PubMed
Summary
This summary is machine-generated.

This study introduces a new scan correlation-aware clustering method to reduce power consumption during cryptographic circuit testing in wireless sensor networks (WSNs). The approach effectively lowers test power, enhancing WSN security and data integrity.

Keywords:
cryptographydesign for testability (DFT)low-power testingscan chain reorderingwireless sensor networks

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Area of Science:

  • Electrical Engineering
  • Computer Engineering
  • Cybersecurity

Background:

  • Cryptographic circuits are vital for wireless sensor network (WSN) security.
  • Manufacturing tests use scan architectures to ensure circuit quality and testability.
  • High test-power consumption is a challenge in complex chip designs.

Purpose of the Study:

  • To address the challenge of significant power reduction during scan testing without excessive computational time.
  • To propose a novel scan correlation-aware scan cluster reordering method for low-power testing.
  • To improve the reliability and security of cryptographic circuits in WSNs.

Main Methods:

  • Developed a novel scan correlation-aware clustering technique.
  • Grouped highly correlated scan cells together within the scan chain.
  • Implemented a scan chain reordering strategy based on the clustering.

Main Results:

  • Achieved significant test-power reduction in cryptographic circuits.
  • Demonstrated a relatively fast computational time compared to existing methods.
  • Validated the effectiveness of the proposed scan correlation-aware clustering.

Conclusions:

  • The proposed method offers an effective solution for reducing test-power consumption in WSN cryptographic circuits.
  • This approach enhances the security and integrity of information transmitted in WSNs.
  • The method balances power reduction with computational efficiency.