Low-Latency QC-LDPC Encoder Design for 5G NR.

Area of Science:

• Electrical Engineering
• Computer Engineering
• Telecommunications

Background:

• 5th generation (5G) New Radio (NR) demands low latency and high throughput for data transmission.
• Minimizing encoder hardware latency and base station power consumption within a fixed transmission time interval (TTI) is crucial for 5G NR.

Purpose of the Study:

• To investigate the parallel design and implementation of a 5G quasi-cyclic low-density parity-check (QC-LDPC) codes encoder.
• To achieve reduced encoding latency and lower power consumption for 5G NR systems.

Main Methods:

• A multi-channel parallel structure was employed for the QC-LDPC encoder design to generate multiple parity check bits.
• High parallelism encoding algorithms were mapped to a configurable circuit architecture, ensuring flexibility for all 5G NR code lengths and rates.

Main Results:

• The designed encoder achieved data throughput ranging from 62 to 257.9 Gbps at an 800 MHz system frequency.
• The maximum encoding time for the longest code length under base graph 1 (BG1) was measured at 33.75 ns.
• Synthesis on SMIC 28 nm CMOS technology validated the encoder's effectiveness and feasibility.

Conclusions:

• The proposed parallel QC-LDPC encoder significantly reduces encoding latency, meeting 5G NR requirements.
• The flexible and efficient design supports diverse 5G NR parameters and demonstrates practical feasibility through silicon synthesis.