Real-Time FPGA Accelerated Stereo Matching for Temporal Statistical Pattern Projector Systems

Area of Science:

• Computer Vision
• Hardware Acceleration
• 3D Measurement Systems

Background:

• Temporal statistical pattern projectors are increasingly used in modern 3D measurement systems for active illumination.
• Stereo vision systems benefit from these patterns due to simplified projector design and no need for pattern characteristic information.
• Real-time stereo matching is computationally intensive, typically requiring Graphics Processing Unit (GPU) solutions.

Purpose of the Study:

• To develop a hardware-accelerated Field Programmable Gate Array (FPGA)-based solution for real-time stereo matching.
• To optimize stereo matching for temporal statistical pattern projector systems.
• To achieve energy-efficient, high-throughput disparity image calculation.

Main Methods:

• Leveraged high-level synthesis (HLS) for FPGA design.
• Implemented matching cost simplification and FPGA-specific optimizations.
• Tested various design configurations on an embedded FPGA platform (ZC706).

Main Results:

• Developed an energy-efficient stereo-matching solution operating at 8.1 W.
• Achieved real-time disparity image calculation for 1024 × 1024 input streams at 291 FPS.
• Demonstrated an average performance-per-watt that was two times higher than GPU-based solutions.

Conclusions:

• The FPGA-based solution offers a significant improvement in performance-per-watt for real-time stereo matching.
• This hardware acceleration provides an energy-efficient alternative to GPU solutions for 3D measurement systems.
• The developed design enables high-throughput and power-efficient 3D data acquisition.