A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Embedded Systems

Background:

• Deep neural networks (DNNs) show promise for feature extraction on edge devices.
• Micro-controller limitations hinder real-time DNN inference due to high computational demands.
• Optimizing DNN inference for low power, low latency, and flexible configuration is critical for sensing systems.

Purpose of the Study:

• To propose a lightweight, pipeline-integrated deep learning architecture for edge devices.
• To enhance DNN inference acceleration compatible with open-source RISC-V instructions.
• To balance performance metrics including low power consumption and low latency.

Main Methods:

• Developed a lightweight pipeline-integrated deep learning architecture.
• Organized DNN dataflow using a very long instruction word (VLIW) pipeline.
• Integrated special intelligent enhanced instructions and a single instruction multiple data (SIMD) unit.

Main Results:

• Achieved a total power consumption of approximately 411 mW.
• Demonstrated a power efficiency of about 320.7 GOPS/W.
• Enabled real-time DNN inference on micro-controller-class processors.

Conclusions:

• The proposed architecture effectively accelerates DNN inference on edge devices.
• The RISC-V compatible design meets critical performance metrics for sensing applications.
• This approach offers a viable solution for power-efficient, real-time edge AI.