Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions

Area of Science:

• Computer Vision
• Hardware Acceleration
• Deep Learning

Background:

• Convolutional Neural Networks (CNNs) are crucial for computer vision tasks.
• Super-resolution CNNs utilize convolutional (CONV) and transposed convolutional (TCONV) layers.
• Real-time and low-power demands drive CNN deployment on Field Programmable Gate Arrays (FPGAs).

Purpose of the Study:

• To present a novel hardware-oriented algorithm for accelerating CONV and TCONV operations.
• To reduce computational operations for efficient CNN deployment.
• To improve the performance of CNNs on hardware platforms like FPGAs.

Main Methods:

• Developed a hardware-oriented algorithm to accelerate both CONV and TCONV layers.
• Integrated the algorithm into a reconfigurable hardware accelerator.
• Designed the accelerator for adaptive run-time operating modes.

Main Results:

• Achieved a throughput of up to 2022.2 GOPS on a Xilinx XC7K410T FPGA.
• Demonstrated up to 2.3 times higher energy efficiency compared to state-of-the-art methods.
• Maintained overall accuracy without compromise.

Conclusions:

• The proposed algorithm efficiently accelerates CONV and TCONV operations for CNNs.
• The reconfigurable hardware accelerator offers significant performance and energy efficiency gains.
• This approach is suitable for demanding real-time and low-power computer vision applications.