Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Acceleration

Background:

• Convolutional and deconvolutional neural networks are vital for computer vision but demand high computational power and memory.
• Designing efficient hardware architectures for these networks, especially for resource-constrained embedded systems, remains a significant challenge.
• Existing solutions struggle with high complexity and memory requirements, hindering widespread adoption.

Purpose of the Study:

• To present a novel, purpose-designed hardware accelerator specifically for 2D deconvolutions.
• To overcome the computational and memory limitations of traditional deconvolution methods.
• To enable efficient deployment of deconvolutional neural networks in embedded systems.

Main Methods:

• Developed a hardware-oriented computational approach for 2D deconvolutions.
• Designed a scalable architecture suitable for Field-Programmable Gate Array (FPGA) based System-on-Chip (SoC) devices.
• Implemented and evaluated the accelerator on Xilinx Zynq XC7Z020 and Virtex-7 XC7VX690T devices.

Main Results:

• The accelerator achieves up to 72 GOPs on a standalone Xilinx Zynq XC7Z020, consuming less than 500mW@200MHz.
• An embedded system with the accelerator performs up to 54 GOPs and dissipates less than 1.8W@150MHz.
• Achieved over 900 GOPs on a Virtex-7 device and demonstrated superior performance and resource efficiency compared to state-of-the-art competitors.

Conclusions:

• The proposed hardware accelerator offers a scalable and efficient solution for 2D deconvolutions in embedded systems.
• It significantly enhances computational capability while reducing power consumption and logic resource utilization.
• The design is suitable for both high- and low-end FPGA-based devices, paving the way for advanced AI applications in edge computing.