Design of a BIST implemented AES crypto-processor ASIC

Area of Science:

• Computer Engineering
• Cryptography
• Integrated Circuit Design

Background:

• The Advanced Encryption Standard (AES) is a highly secure symmetric encryption algorithm, favored for hardware implementations due to superior speed and security.
• Existing AES cryptoprocessor Application Specific Integrated Circuits (ASICs) lack adequate testability solutions for their complex architectures.

Purpose of the Study:

• To address the critical issue of testability in AES cryptoprocessor ASICs.
• To propose and validate a novel Built-in-self-Test (BIST) methodology for AES hardware.

Main Methods:

• Design and implementation of a mixed-mode BIST technique, combining pseudo-random and deterministic approaches.
• Development of the AES cryptoprocessor ASIC using a Hardware Description Language (HDL).
• Simulation and validation using Electronic Design Automation (EDA) tools and National Institute of Standards and Technology (NIST) data.

Main Results:

• The designed BIST-implemented AES cryptoprocessor ASIC functions correctly across various operational modes.
• Simulation results confirm the effectiveness of the mixed-mode BIST approach for AES ASIC testability.
• The proposed BIST implementation is unique compared to existing research in AES cryptoprocessor ASICs.

Conclusions:

• The developed mixed-mode BIST effectively resolves the testability challenges in AES cryptoprocessor ASICs.
• This research offers a significant advancement in the design and verification of secure and testable cryptographic hardware.
• The findings pave the way for more robust and reliable hardware security solutions.