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Updated: Oct 11, 2025

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
Published on: August 28, 2018
First demonstration of robust tri-gateβ-Ga2O3nano-membrane field-effect transistors
Hagyoul Bae1,2, Tae Joon Park3, Jinhyun Noh1,2
1Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, United States of America.
Abstract:
Nano-membrane tri-gateβ-gallium oxide (β-Ga2O3) field-effect transistors (FETs) on SiO2/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized features can be defined with the footprint channel width of 50 nm. For high-quality interface betweenβ-Ga2O3and gate dielectric, atomic layer-deposited 15 nm thick aluminum oxide (Al2O3) was utilized with tri-methyl-aluminum (TMA) self-cleaning surface treatment. The fabricated devices demonstrate extremely low subthreshold slope (SS) of 61 mV dec-1, high drain current (IDS) ON/OFF ratio of 1.5 × 109, and negligible transfer characteristic hysteresis. We also experimentally demonstrated robustness of these devices with current-voltage (I-V) characteristics measured at temperatures up to 400 °C.
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