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Related Concept Videos

Fermi Level Dynamics01:12

Fermi Level Dynamics

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The vacuum level denotes the energy threshold required for an electron to escape from a material surface. It is usually positioned above the conduction band of a semiconductor and acts as a benchmark for comparing electron energies within various materials.
Electron affinity in semiconductors refers to the energy gap between the minimum of its conduction band and the vacuum level and it is a critical parameter in determining how easily a semiconductor can accept additional electrons.
The work...
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Fermi Level01:18

Fermi Level

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The Fermi-Dirac function is represented by an S-shaped curve indicating the probability of an energy state being occupied by an electron at a given temperature. The Fermi level is the energy level at which there is a fifty percent chance of finding an electron, and it is positioned between the lower-energy valence band and the higher-energy conduction band.
At absolute zero temperature, electrons fill all energy states up to the Fermi level, leaving upper states empty. As the temperature rises,...
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Metal-Semiconductor Junctions01:24

Metal-Semiconductor Junctions

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The contact of metal and semiconductor can lead to the formation of a junction with either Schottky or Ohmic behavior.
Schottky Barriers
Schottky barriers arise when a metal with a work function (Φm) contacts a semiconductor with a different work function (Φs). Initially, electrons transfer until the Fermi levels of the metal and semiconductor align at equilibrium. For instance, if Φm > Φs, the semiconductor Fermi level is higher than the metal's before contact. The...
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Biasing of Metal-Semiconductor Junctions01:27

Biasing of Metal-Semiconductor Junctions

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Biasing metal-semiconductor junctions involves applying a voltage across the junction. Specifically, the metal is connected to a voltage source, while the semiconductor is grounded. This technique is essential for controlling the direction and magnitude of current flow in electronic devices, including diodes, transistors, and photovoltaic cells.
In Schottky junctions, where the semiconductor is n-type, applying a positive voltage to the metal relative to the semiconductor reduces its Fermi...
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Types of Semiconductors01:20

Types of Semiconductors

1000
Intrinsic semiconductors are highly pure materials with no impurities. At absolute zero, these semiconductors behave as perfect insulators because all the valence electrons are bound, and the conduction band is empty, disallowing electrical conduction. The Fermi level is a concept used to describe the probability of occupancy of energy levels by electrons at thermal equilibrium. In intrinsic semiconductors, the Fermi level is positioned at the midpoint of the energy gap at absolute zero. When...
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P-N junction01:11

P-N junction

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A p-n junction is formed when p-type and n-type semiconductor materials are joined together. At the interface of the p-n junction, holes from the p-side and electrons from the n-side begin to diffuse into the opposite sides due to the concentration gradient. This diffusion of carriers leads to a region around the junction where there are no free charge carriers, known as the depletion region. The charge density within the depletion region for the n-side and p-side can be described by the...
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Fermi Level Pinning Dependent 2D Semiconductor Devices: Challenges and Prospects.

Xiaochi Liu1, Min Sup Choi2, Euyheon Hwang2

  • 1School of Physics and Electronics, Central South University, Changsha, 410083, China.

Advanced Materials (Deerfield Beach, Fla.)
|December 16, 2021
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Fermi level pinning (FLP) in 2D materials hinders device performance. This study explores FLP origins in 2D semiconductors and offers strategies for improved metallic contacts, crucial for future electronic devices.

Keywords:
2D semiconductorsFermi level pinningelectrical contactsfield-effect transistorsinterface gap states

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Area of Science:

  • Materials Science
  • Condensed Matter Physics
  • Nanotechnology

Background:

  • Atomically thin 2D materials are promising for next-generation semiconductor devices due to efficient electrostatic modulation.
  • The van der Waals (vdW) structure of 2D materials presents processing challenges, including Fermi level pinning (FLP) at metal interfaces.
  • Unmodulated semiconductor polarity, high contact resistance, and reduced mobility are consequences of FLP in 2D devices.

Purpose of the Study:

  • To address Fermi level pinning (FLP) in 2D semiconductor devices, distinct from conventional semiconductors.
  • To investigate the origins of FLP in 2D materials, including inefficient doping, vdW gaps, and metal-induced compound formation.
  • To provide practical guidelines for designing 2D devices by reviewing FLP's impact and mitigation strategies.

Main Methods:

  • Review of FLP phenomena in recently developed 2D semiconductor devices.
  • Analysis of factors contributing to FLP: doping efficiency, interface vdW gaps, and metal-semiconductor interactions.
  • Exploration of methods to improve metallic contacts to 2D materials.

Main Results:

  • Identified FLP in 2D materials is attributed to unique factors like inefficient doping and interface characteristics.
  • Demonstrated that FLP significantly impacts 2D device performance, including contact resistance and mobility.
  • Highlighted the necessity of addressing FLP for effective 2D device design and fabrication.

Conclusions:

  • Understanding and mitigating FLP is critical for unlocking the full potential of 2D semiconductor devices.
  • Strategies for improving metallic contacts are essential for overcoming performance limitations imposed by FLP.
  • This review offers valuable insights for researchers and engineers working on 2D electronic devices.