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An application-specific image processing array based on WSe2 transistors with electrically switchable logic

Senfeng Zeng1, Chunsen Liu2,3, Xiaohe Huang1

  • 1State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, 200433, Shanghai, China.

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|January 11, 2022
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Summary
This summary is machine-generated.

Researchers developed a novel pixel processing unit using a single WSe2 transistor. This design enables efficient parallel image processing with reduced circuit redundancy and lower transistor consumption for AI hardware.

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Area of Science:

  • Materials Science
  • Computer Engineering
  • Artificial Intelligence

Background:

  • Parallel image processing is crucial for artificial intelligence (AI) hardware.
  • Traditional pixel processing units exhibit circuit redundancy, limiting optimization.
  • Area redundancy in parallel computing presents a significant challenge.

Purpose of the Study:

  • To develop a highly efficient pixel processing unit.
  • To reduce transistor consumption in image processing arrays.
  • To demonstrate a novel approach for parallel image processing using advanced materials.

Main Methods:

  • Fabrication of a pixel processing unit utilizing a single Tungsten Diselenide (WSe2) transistor.
  • Integration of these units into a low transistor-consumption image processing array.
  • Demonstration of electrically switchable multiple logic functions (AND, XNOR) within the unit.

Main Results:

  • The WSe2 transistor-based unit exhibits multiple logic functions (AND, XNOR).
  • The integrated image processing array performs image intersection and comparison tasks.
  • Transistor consumption is reduced to less than 16% compared to traditional circuits for equivalent processing power.

Conclusions:

  • A novel, area-efficient pixel processing unit based on WSe2 transistors has been demonstrated.
  • This technology significantly reduces transistor count for parallel image processing in AI.
  • The proposed design offers a promising solution for optimizing computing hardware for AI applications.