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Updated: Jan 14, 2026

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures

Published on: December 5, 2015

Wafer-scale monolayer dielectric integration on atomically thin semiconductors.

Zhenzhen Shen¹, Haoqi Wu¹, Chunsen Liu²

¹State Key Laboratory of Integrated Chips and Systems, College of Integrated Circuits and Micro-Nano Electronics, Frontier Institute of Chip and System, Zhangjiang Fudan International Innovation Center, Fudan University, Shanghai, China.

Nature Materials

|January 12, 2026

Summary

Researchers developed a novel wafer-scale monolayer molybdenum trioxide (MoO3) dielectric for ultrathin transistors. This breakthrough enables robust integration with 2D materials, achieving sub-nanometer capacitance equivalent thickness (CET) for enhanced device performance and scalability.

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Published on: July 18, 2025

Area of Science:

Materials Science
Semiconductor Physics
Nanotechnology

Background:

Miniaturizing metal-oxide-semiconductor field-effect transistors (MOSFETs) requires ultrathin two-dimensional (2D) channel materials.
Integrating dielectrics with sub-1-nm capacitance equivalent thickness (CET) on 2D materials is a significant challenge.
Existing methods struggle to achieve uniform and robust dielectric layers on atomically thin semiconductors.

Purpose of the Study:

To develop a scalable method for integrating ultralow-CET dielectrics on 2D materials.
To demonstrate the effectiveness of a novel dielectric material for advanced transistor fabrication.
To enable the industrial deployment of 2D material-based transistors.

Main Methods:

Wafer-scale synthesis of monolayer molybdenum trioxide (MoO3) via transformation from molybdenum disulfide (MoS2).
Seamless integration of MoO3 with atomically thin semiconductors.
Deposition of high-κ dielectrics (e.g., HfO2) on the atomically flat MoO3 surface.
Fabrication and characterization of top-gated 2D transistors utilizing the MoO3/HfO2 dielectric stack.

Main Results:

Achieved a sub-1-nm CET (0.96 nm) using MoO3/HfO2 dielectric on 2D transistors.
Demonstrated high ON/OFF ratios (6.5 × 10^6 for p-type, 3.2 × 10^8 for n-type) and steep subthreshold swings (60.8 mV/dec for p-type, 63.1 mV/dec for n-type).
Verified high device yield (92.2%) across a 1,024-device array.
Utilized monolayer MoO3 as a top-gated dielectric with an ultra-scaled CET of 0.64 nm, meeting low-power leakage standards (1.5 × 10^-2 A/cm^2).

Conclusions:

Monolayer MoO3 provides a scalable pathway for integrating ultralow-CET dielectrics with 2D materials.
The developed dielectric integration strategy significantly enhances the performance of 2D transistors.
This work represents a critical advancement towards the industrial application of 2D semiconductor devices.