Mixed-Dimensional 1D/2D van der Waals Heterojunction Diodes and Transistors in the Atomic Limit

Area of Science:

• Materials Science
• Nanotechnology
• Semiconductor Physics

Background:

• Field-effect transistor (FET) operation relies on inverting a semiconducting channel.
• Silicon-based metal-oxide-semiconductor FETs (MOSFETs) use a gate dielectric for inversion.
• Advancing device downscaling requires new methods for accessing inversion layers, such as using ultrathin low-dimensional semiconductors in heterojunctions.

Purpose of the Study:

• To demonstrate a novel transistor architecture using a 1D/2D van der Waals heterojunction.
• To show that monolayer molybdenum disulfide (MoS2) can directly invert a single-walled semiconducting carbon nanotube (SWCNT) channel without a gate dielectric.
• To investigate the characteristics and potential of this new transistor design for future electronic devices.

Main Methods:

• Fabrication of an atomically thin 1D/2D van der Waals heterojunction between MoS2 and SWCNT.
• Utilizing the MoS2/SWCNT heterojunction as the gate for a 1D heterojunction field-effect transistor (1D-HFET).
• Characterization of the 1D-HFET's electrical properties, including gate control and tunneling current.
• Technology computer-aided design (TCAD) simulations to model device behavior.

Main Results:

• Successful demonstration of MoS2 directly inverting the SWCNT channel, forming a 1D-HFET.
• Gate control achieved by modulating conductance via a lateral p-n junction within the CNT.
• Observation of negative static resistance due to minority carrier drift-diffusion, confirmed by TCAD simulations.
• The van der Waals transistor exhibits both field-effect and tunneling transistor characteristics.

Conclusions:

• The developed van der Waals transistor architecture bypasses the need for gate dielectrics, enabling further device downscaling.
• This 1D/2D heterojunction approach overcomes limitations associated with dangling bonds and epitaxial constraints in traditional semiconductor manufacturing.
• The device represents a significant advancement in heterostructure design, merging FET and tunneling transistor functionalities.