Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs.

Area of Science:

• Semiconductor device physics
• Materials science
• Computational modeling

Background:

• Down-scaling of field-effect transistors (FETs) presents challenges in power management.
• Gate-all-around (GAA) FET architectures are crucial for future integrated circuits.
• Electro-thermal annealing (ETA) is a key process step in semiconductor manufacturing.

Purpose of the Study:

• To investigate device guidelines for reducing power consumption during punch-through current annealing in GAA FETs.
• To analyze the impact of geometric dimensions and materials on heat management during down-scaling.
• To identify optimal engineering strategies for maximizing power efficiency in GAA FETs.

Main Methods:

• Three-dimensional (3D) simulations were employed to model GAA FETs.
• Systematic variation of geometric dimensions and material properties was performed.
• Electro-thermal simulations were conducted to assess heat dissipation and power consumption.

Main Results:

• Gate module engineering demonstrated superior effectiveness in managing heat compared to isolation or source/drain module engineering.
• Specific geometric and material parameters were identified as critical for optimizing thermal performance.
• Power reduction strategies were validated through simulation under various down-scaling scenarios.

Conclusions:

• Gate module engineering is a highly suitable strategy for maximizing power efficiency during ETA in GAA FETs.
• Understanding the interplay between device geometry, materials, and thermal management is essential for advanced semiconductor design.
• The findings provide valuable guidelines for the development of energy-efficient GAA FETs.