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Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs
Min-Kyeong Kim1, Yang-Kyu Choi2, Jun-Young Park1
1School of Electronics Engineering, Chungbuk National University, Chungdae-ro 1, Chungbuk, Cheongju 28644, Korea.
Abstract:
Device guidelines for reducing power with punch-through current annealing in gate-all-around (GAA) FETs were investigated based on three-dimensional (3D) simulations. We studied and compared how different geometric dimensions and materials of GAA FETs impact heat management when down-scaling. In order to maximize power efficiency during electro-thermal annealing (ETA), applying gate module engineering was more suitable than engineering the isolation or source drain modules.
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