Hierarchical Network Connectivity and Partitioning for Reconfigurable Large-Scale Neuromorphic Systems

Area of Science:

• Neuroscience
• Computer Science
• Hardware Engineering

Background:

• Scalability in computational efficiency is a major challenge for very large neural networks.
• Existing partitioning algorithms struggle with optimizing network workloads and hardware mapping.
• Communication overhead is a significant bottleneck in distributed processing for neural networks.

Purpose of the Study:

• To present an efficient and scalable partitioning method for mapping large-scale neural network models onto reconfigurable neuromorphic hardware.
• To optimize partitioning for compute-balanced, memory-efficient parallel processing with minimal routing.
• To address the challenges of computational efficiency and network workload scalability in large networks.

Main Methods:

• Developed a partitioning framework optimized for low-latency execution and dense synaptic storage.
• Implemented connectivity-aware and hierarchical address-event routing for resource-optimized mapping.
• Evaluated the method on synthetic networks, small-world networks, feed-forward networks, and a fruit-fly brain hemibrain reconstruction.

Main Results:

• Demonstrated highly scalable and efficient partitioning, significantly reducing total communication volume recursively compared to random assignment.
• Achieved compute-balanced, memory-efficient parallel processing with minimal routing across compute cores.
• Showcased successful application on diverse network types, including biological connectomes.

Conclusions:

• The proposed partitioning method offers a promising approach for extending to very large-scale neural networks.
• The framework enables scalable, hardware-aware partitioning crucial for efficient neuromorphic computing.
• Optimized communication and computation balance leads to significant performance improvements.