Hardware Implementation of a Fixed-Point Decoder for Low-Density Lattice Codes.

Area of Science:

• Digital Signal Processing
• Error Correction Coding
• Hardware Implementation

Background:

• Iterative decoding algorithms like LDLC are crucial for reliable communication.
• Floating-point implementations of decoders can be resource-intensive.
• Fixed-point implementations offer potential for reduced hardware complexity and power consumption.

Purpose of the Study:

• To develop and evaluate a fixed-point low-density lattice code (LDLC) decoder on a field-programmable gate array (FPGA).
• To optimize the decoder for efficient hardware implementation by approximating Gaussian mixture messages.
• To analyze the trade-offs between performance, resource utilization, and throughput for different decoder architectures.

Main Methods:

• A detailed quantization study was conducted to determine the optimal fixed-point precision for achieving performance comparable to floating-point decoders.
• Efficient numerical methods were devised to approximate non-linear functions within the decoding process.
• A novel pipelined LDLC decoder architecture was proposed, incorporating resource re-utilization and pipelining for enhanced parallelism.

Main Results:

• The fixed-point decoder achieved frame error rate (FER) performance similar to floating-point implementations.
• The proposed pipelined architecture demonstrated parallelism equivalent to 50 variable nodes on the FPGA.
• A throughput of 10.5 Msymbols/sec was achieved at 5 dB from capacity, representing a significant improvement over non-pipelined and serial decoders.

Conclusions:

• Fixed-point LDLC decoders can be efficiently implemented on FPGAs with minimal performance degradation.
• The novel pipelined architecture offers substantial throughput gains, making it suitable for high-speed communication systems.
• The study provides valuable insights into hardware-software co-design for advanced error correction codes.