Defect Engineering in Thickness-Controlled Bi₂O₂Se-Based Transistors by Argon Plasma Treatment

We present a simple, effective, and controllable method to uniformly thin down the thickness of as-exfoliated two-dimensional Bi₂O₂Se nanoflakes using Ar⁺ plasma treatment. Atomic force microscopy (AFM) images and Raman spectra indicate that the surface morphology and crystalline quality of etched Bi₂O₂Se nanoflakes remain almost unaffected. X-ray photoelectron spectra (XPS) indicate that the O and Se vacancies created during Ar⁺ plasma etching on the top surface of Bi₂O₂Se nanoflakes are passivated by forming an ultrathin oxide layer with UV O₃ treatment. Moreover, a bottom-gate Bi₂O₂Se-based field-effect transistor (FET) was constructed to research the effect of thicknesses and defects on electronic properties. The on-current/off-current (I_on/I_off) ratio of the Bi₂O₂Se FET increases with decreasing Bi₂O₂Se thickness and is further improved by UV O₃ treatment. Eventually, the thickness-controlled Bi₂O₂Se FET achieves a high I_on/I_off ratio of 6.0 × 10⁴ and a high field-effect mobility of 5.7 cm² V^-1 s^-1. Specifically, the variation trend of the I_on/I_off ratio and the electronic transport properties for the bottom-gate Bi₂O₂Se-based FET are well described by a parallel resistor model (including bulk, channel, and defect resistance). Furthermore, the I_ds-V_gs hysteresis and its inversion with UV irradiation were observed. The pulsed gate and drain voltage measurements were used to extract trap time constants and analyze the formation mechanism of different hysteresis. Before UV irradiation, the origin of clockwise hysteresis is attributed to the charge trapping/detrapping of defects at the Bi₂O₂Se/SiO₂ interface and in the Bi₂O₂Se bulk. After UV irradiation, the large anticlockwise hysteresis is mainly due to the tunneling between deep-level oxygen defects in SiO₂ and p⁺⁺-Si gate, which implies the potential in nonvolatile memory.