Compression of Deep Neural Networks based on quantized tensor decomposition to implement on reconfigurable hardware...

Area of Science:

• Artificial Intelligence
• Machine Learning
• Computer Engineering

Background:

• Deep Neural Networks (DNNs) offer advanced capabilities in AI but face challenges with high computational and memory demands.
• Limited internal memory on processing platforms necessitates external storage, hindering DNN deployment on resource-constrained devices like mobile applications.
• Existing DNNs require substantial parameters, leading to significant computational costs and memory consumption.

Purpose of the Study:

• To develop a parameter compression method for DNNs to reduce memory footprint and computational costs.
• To enable efficient deployment of DNNs on mobile applications and hardware accelerators like FPGAs.
• To maintain network accuracy and structure during the compression process.

Main Methods:

• Employed tensor decomposition to compress DNN weight tensors into principal vectors.
• Modified the tensor decomposition algorithm for optimized FPGA realization without affecting convergence.
• Ensured network structure and quality (detection accuracy) remained largely unchanged post-compression.

Main Results:

• Achieved significant parameter reduction, compressing ResNet50, VGG16, and VGG19 networks by approximately 10 times.
• Reduced the need for external memory access by compressing network parameters.
• Demonstrated straightforward reproduction of compressed network parameters on FPGAs.

Conclusions:

• Tensor decomposition offers an effective strategy for compressing DNN parameters, addressing memory and computational challenges.
• The proposed method facilitates the deployment of complex DNNs on mobile and edge devices.
• Optimized tensor decomposition enables efficient hardware implementation on FPGAs while preserving network performance.