A Low-Latency Divider Design for Embedded Processors.

Area of Science:

• Computer Engineering
• Digital Logic Design
• Embedded Systems

Background:

• Integer division is a critical but often slow operation in embedded processors, frequently causing pipeline stalls.
• Existing division algorithms present challenges in terms of latency, iteration count, and resource utilization.
• High-performance embedded systems demand efficient division operations to maintain overall processor speed.

Purpose of the Study:

• To design and implement a low-delay divider specifically for embedded processors.
• To enhance the performance of integer division operations by reducing latency and iteration cycles.
• To create a division solution that offers significant improvements in speed, area, and power efficiency.

Main Methods:

• The divider is based on the non-restoring algorithm, incorporating a compound adder for simultaneous addition and subtraction.
• Operand shifting is employed to align significant bits, dynamically adjusting iteration cycles.
• The design was simulated using Modelsim and verified on an FPGA, then synthesized using a 65 nm Low Leakage process.

Main Results:

• The synthesized design achieved a frequency of up to 500 MHz with an area cost of 5670.36 μm².
• Achieved up to 45.3% reduction in single iteration delay and 20-50% saving in average iteration cycles.
• Demonstrated significant area savings (23.3-86.1%) and FPGA resource reduction (36.47-59.6% LUTs, 67-84.28% FFs), with a 2-6.36x speed increase.

Conclusions:

• The proposed low-delay divider offers substantial improvements in performance and resource efficiency for embedded processors.
• The design effectively addresses the challenges of high latency and frequent pipeline stalls associated with division operations.
• This optimized divider is well-suited for embedded applications prioritizing low power, minimal resource usage, and high computational throughput.