Fully Parallel Stochastic Computing Hardware Implementation of Convolutional Neural Networks for Edge Computing...

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Architecture

Background:

• Edge artificial intelligence (AI) is increasingly popular with the Internet of Things (IoT).
• Deep learning techniques like Convolutional Neural Networks (CNNs) are power- and area-intensive for edge devices.
• Implementing AI on edge devices faces challenges in power consumption, resource utilization, and accuracy.

Purpose of the Study:

• To propose a power- and area-efficient architecture for edge AI.
• To leverage stochastic computing (SC) and its correlation phenomenon for efficient CNN implementation.
• To address challenges in SC-CNNs, including conversion, signal correlation, and stochastic function complexity.

Main Methods:

• Developed a novel architecture exploiting the correlation phenomenon in stochastic computing (SC).
• Implemented a fully parallel CNN using the proposed SC architecture on a Field-Programmable Gate Array (FPGA).
• Conducted VLSI synthesis to evaluate the design's characteristics against existing architectures.

Main Results:

• The proposed SC-CNN architecture demonstrated superior performance compared to traditional binary logic and other SC implementations.
• The FPGA implementation confirmed the architecture's suitability for edge intelligence.
• VLSI synthesis indicated better overall characteristics than recently published VLSI architectures.

Conclusions:

• The proposed SC-based architecture offers a power- and area-efficient solution for implementing CNNs on edge devices.
• This approach effectively overcomes key challenges associated with SC-CNNs.
• The design shows significant promise for realizing efficient edge AI applications.