Minimizing Global Buffer Access in a Deep Learning Accelerator Using a Local Register File with a Rearranged...

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Acceleration

Background:

• Deep learning accelerators are crucial for AI, but high power consumption from global buffer access is a major challenge.
• Efficient data reuse is key to reducing energy demands in these accelerators.

Purpose of the Study:

• To propose a novel deep learning accelerator architecture that minimizes global buffer access for convolution operations.
• To enhance energy efficiency by maximizing data reuse through a shared local register file.

Main Methods:

• A rearranged computational sequence to exploit data reuse opportunities.
• Implementation of a shared local register file across computation units in a 2D array.
• Verification on a field-programmable gate array (FPGA) and performance comparison with existing accelerators.

Main Results:

• Reduced global buffer accesses by 86.8%.
• Achieved up to 72.3% power saving in input data memory access.
• Demonstrated minor increase in resource usage compared to conventional accelerators.

Conclusions:

• The proposed accelerator design significantly enhances energy efficiency for deep learning computations.
• Shared local register files offer a viable strategy for resource and power optimization in AI hardware.
• This approach provides a practical solution for power-hungry deep learning workloads.